With the development of integrated circuitry and, in particular, MOS/VLSI technology in combination with more circuitry on a chip, there is a standing and ever increasing desire to be able to provide complete digital on-chip self-calibrated timing and clocking of signals employed in such circuitry.
Presently, signal timing or desired clock generation is provided by off-chip or separate or discrete integrated circuitry utilizing various conventional techniques for such generation schemes, such as one shot multivibrators, phase locked loop (PLL) arrangements and discrete signal and clock generation provided in bipolar technology. In these cases, some analog arrangement is made to check the timing or clocking period to determine that it is continually correct. Such checking is done periodically so that it may or may not be continuously accurate. As a result, timing or clocking may not always be accurate in circuit utilization, resulting in malfunctioning or loss of data. What is desired is clocking and timing circuitry that is on-chip with the integrated circuitry and is somehow self-calibrated to continuously maintain timing accuracy.
If one depends on analog values in on-chip clocking and timing, many problems are encountered because of changes that occur in physical and electrical properties in the successive processing of wafers. Uniformity in clock and signal timing generation from wafer to wafer is crucial where precise product specifications must be met and if clocking and signal timing generation properties must depend upon fabricated circuit parameters, uniformity in those properties from batch processing is next to impossible in MOS technology, e.g., nMOS. Presently, complex timing interface circuitry is employed to provide clocking and timing signals and means to verify the accuracy of such signals before applying them to perform their designated regulatory functioning. However, there is not a presently realizable methodology as to how to implement their functioning in MOS/VLSI technology, e.g., nMOS with verified accuracy and know precisely when the time occurrence of a signal transitional edge will occur and what the resolution will be between transitional edge occurrences in nMOS implemented clocking and timing.
It is the primary objective of this invention to provide self-calibrated clock and signal timing generation in MOS technology independent of significance of physical and electrical properties derived in successive integrated circuit processing.